1. Field
Aspects of the present disclosure relate generally to memory, and more particularly, to programmable power for a memory interface.
2. Background
A chip may include a memory interface for interfacing circuits (e.g., a memory controller) on the chip with an external memory device, such as a double data rate dynamic random access memory (DDR DRAM). The memory interface may include delay circuits for adjusting the timing of signals (e.g., data signals) in the memory interface. For example, the memory interface may include delay circuits to compensate for skew between data signals (e.g., due to mismatches in the lengths of data lines between the memory interface and the external memory device). In another example, the memory interface may include a delay circuit to center a data strobe signal used for data sampling between transitions of the data signals.